The present invention generally relates to resistive switching devices (RSDs). More specifically, the present invention relates to fabrication methodologies and resulting structures for forming vertical resistive random access memory (ReRAM) cells that reduce the metal resistance of the vertical and lateral electrodes.
ReRAM is a nano-scale non-volatile memory (NVM). ReRAM provides simple storage cell components, high density, low power, large endurance, fast write, read and erase speeds, and excellent scalability. A typical ReRAM storage cell is two-terminal device formed as a metal-insulator-metal (MIM) structure. The insulator material can be a binary metal oxide, which makes the MIM storage cell compatible with silicon-based CMOS (complementary metal oxide semiconductor) fabrication process. When a sufficient electrical signal is applied across the metal electrodes of a MIM, the resistance of the insulator can be switched from one resistance state to another. The insulator retains its current resistance state until an appropriate electrical signal is applied across the metal electrodes to change it.
ReRAM, along with the logic circuitry used to address, read and write individual ReRAM cells, can be implemented in an array (e.g., a ReRAM cell array), which is compatible with a variety of electronic circuits and devices, including neuromorphic architectures. Multiple pre-neurons and post-neurons can be connected through the array of ReRAMs, which naturally expresses a fully-connected neural network. The density of ReRAM can be increased by configuring the array as a three-dimensional (3D) vertical stack of addressable ReRAM cells as practiced in Flash NAND technologies.